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CX24118A
Advanced Modulation Digital Satellite Tuner
Rev. 02 -- 8 September 2009 Product data sheet
Document information Info Keywords Abstract Content
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
Ordering information
Type number
CX24118A-12Z*
Description
Advanced Modulation Digital Satellite Tuner 36-pin QFN
Package
*Lead-free (Pb Free) and RoHS compliant
Revision history
Revision
02 01 20090908 20081125
Date
Added Figure 12
Description
First NXP version based on the Conexant 102322A data sheet.
Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
CX24118A_N_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
2
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
General description
The CX24118A is a direct down-conversion satellite tuner intended for high-volume digital video, audio, and data receivers. The CX24118A offers excellent phase noise performance and very low implementation loss, required for advanced modulation systems such as 8PSK and DVB-S2. The CX24118A has a built-in auto-tuning system that eliminates the need for software calibration. The on-chip fractional synthesizer enables fine frequency step size without adversely affecting lock time. The CX24118A does not require a balun, thus reducing external BOM cost. Its highly integrated design saves valuable board space and simplifies RF layout.
Features
Single-chip RF-to-baseband satellite receiver Zero-IF architecture eliminates the need for image reject filtering Very low phase noise integrated Local Oscillators (LOs) for 8PSK and DVB-S2 applications Variable baseband filters for optimal interference rejection Auto-tuning system eliminates need for software calibration Very low power consumption Small (6 mm x 6 mm) footprint Lead-free package
Applications
8PSK, DVB-S2, and advanced modulation set-top boxes Commercial digital video, audio, and PVR receivers
Product Specifications
RF input: 925-2175 MHz Symbol rate: 1-45 MSps Noise figure: 10 dB, typical Input IP3 at minimum gain: 10 dBm, typical
Block diagram
CP_OUT VTUNE
PLL and VCO DC Offset Cancellation Filter 1 VGA1 Filter 2 VGA2 : 2, :4
I/Q Mixer VCA RF_IN 0o 90o
I_OUT Final Amplifier
AGC Control AGC XSEL XTAL1 XTAL2 CKREF_OUT Crystal Oscillator and Clock Control
Q_OUT DC Offset Cancellation Filter Control Logic Interface SDA SCL SADD
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
3
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
4
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
11 11 12 15 15 15 16 17 18 20 20 23 23 26 27 29 37 37 37 37 37 39 39 40 40 40 40 43 45
1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Downconverter and Baseband Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Local Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Crystal Oscillator and Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Automatic Tuning System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Auto-tuning Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Serial Programming Interface and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Serial Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Register Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Thermal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Sleep Mode Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Changing from Normal Operation to Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Changing from Sleep Mode to Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical, Thermal, and Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 S11 Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Electrical and Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Receiver Electrical and Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
5
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
6
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
11 15 18 19 23 24 24 25 26 39 43 44
Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 Fig. 11 Fig. 12
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Divider Settings vs. Frequency When Using 40 MHz Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . Third-Overtone Crystal Oscillator External Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Single-Byte Write Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Multiple-Bytes Write Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Single-Byte Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Multiple-Bytes Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S11 Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
7
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
8
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
12 16 17 19 20 26 27 37 40 40 40
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11.
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Signal Level Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum Signal Level Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Component Values for Third-Overtone Crystal Oscillator External Circuit . . . . . . . . . . . . . . . . Crystal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
9
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
10
CX24118A
Chapter 1: Pin Descriptions
Rev. 02 -- 8 September 2009 Product data sheet
1.1
Figure 1.
Pin Diagram
Figure 1 provides a pinout of the CX24118A.
Pin Diagram
VCC2_RF
VCC_PS
SADD
XSEL
N/C
N/C
N/C
N/C 29
36
35
34
33
32
31
30
N/C VCC_VCO VTUNE VCC_CP CP_OUT XTAL_BIAS VCC_XTAL XTAL1 XTAL2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CX24118A
(Exposed Paddle = Gnd)
28 27 26 25 24 23 22 21 20 19
N/C
N/C RF_INN RF_INP VCC1_RF VCC1_BB AGC VCC2_BB BB_REF N/C
VCC_DIG
CKREF_OUT
GND_DIG
SCL
Q_OUTP
Q_OUTN
I_OUTN
I_OUTP
SDA
102322_002
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
11
NXP Semiconductors
CX24118A
Chapter 1: Pin Descriptions
1.2
Pin Assignments
Table 1 lists the CX24118A pin names, numbers, types, and descriptions.
Table 1.
Pin Assignments
Pin Name
N/C VCC_VCO VTUNE VCC_CP CP_OUT XTAL_BIAS VCC_XTAL XTAL1 XTAL2 CKREF_OUT VCC_DIG GND_DIG SDA SCL I_OUTN I_OUTP Q_OUTP Q_OUTN N/C BB_REF VCC2_BB AGC VCC1_BB VCC1_RF RF_INP
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Type
N/C Power Input Power Output Input Power Input Output Output Power Ground I/O Input Output Output Output Output N/C Input Power Input Power Power Input Not internally connected.
Description
3.3V power supply for the VCO section. VCO tuning voltage input. The output of the external PLL loop filter is connected to this pin. 3.3V power supply for the charge pump section. Charge pump output. The input of the external PLL loop filter is connected to this pin. Crystal oscillator bias. For normal operation, leave this pin unconnected. 3.3V power supply for the crystal oscillator section. Crystal oscillator input pins. Use a 40 MHz or 40.444 MHz third-overtone crystal oscillator circuit. Clock reference output. The maximum load allowed at this pin is 10 k // 20 pF. 3.3 V power supply for digital section. Digital ground. Serial programming interface data signal. Open drain. Serial programming interface clock signal. The negative differential I channel output to demodulator. Zout = 1 k // 10 pF. The positive differential I channel output to demodulator. Zout = 1 k // 10 pF. The positive differential Q channel output to demodulator. Zout = 1 k // 10 pF. The negative differential Q channel output to demodulator. Zout = 1 k // 10 pF. Not internally connected. Current reference for baseband section. Place a 698 1% resistor to ground. 3.3 V power supply for the baseband section. AGC control input from the demodulator, which controls the gain of the RF attenuator and both baseband variable gain amplifiers. Zin = 10 k // 20 pF. 3.3 V power supply for the baseband section. 3.3 V power supply pin for the RF section. The positive differential RF signal input pin.
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
12
NXP Semiconductors
CX24118A
Chapter 1: Pin Descriptions
Table 1.
Pin Assignments
Pin Name
RF_INN N/C N/C N/C N/C VCC2_RF N/C N/C SADD
Pin Number
26 27 28 29 30 31 32 33 34
Type
Input N/C N/C N/C N/C Power N/C N/C I/O
Description
The negative differential RF signal input pin. This pin should be AC grounded with a capacitor to ground. Not internally connected. Not internally connected. Not internally connected. Not internally connected. 3.3 V power supply pin for the RF section. Not internally connected. Not internally connected. Serial address select pin. This pin has an internal pull-up, so an open on this pin will be a logic level high (default address of 54) and a short to ground will be a logic level low (address of 14). Crystal bias select pin. Leave floating for operation with a 40 MHz third-overtone crystal. This pin has an internal 30 k pull-up resistor. 3.3 V power supply for the prescaler section. The exposed paddle at the bottom of the chip is the common chip ground and the thermal conductor.
XSEL VCC_PS Exposed Paddle
35 36
Input Power Ground
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
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NXP Semiconductors
CX24118A
Chapter 1: Pin Descriptions
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
14
CX24118A
Chapter 2: Functional Descriptions
Rev. 02 -- 8 September 2009 Product data sheet
2.1
General Description
The CX24118A is a highly integrated direct conversion tuner requiring a minimum of off-chip components. It incorporates a low-noise amplifier with integrated Voltage Controlled Attenuator (VCA), quadrature down converter, variable bandwidth base-band filter/amplifier, fractional synthesizer, crystal oscillator with buffered output, and an automatic tuning system. The chip is controlled through a multi-byte read/write enabled I2C(R)-compatible interface. A CX24118A detailed block diagram is shown in Figure 2.
Figure 2.
Detailed Block Diagram
DC Offset Cancellation I/Q Mixer Filter 1 VGA1 Filter 2 VGA2 I_OUT VCA RF_IN
0o 90o
Final Amplifier
AGC Control DC Offset Cancellation AGC Filter Control
Q_OUT
LODivSel XSEL XTAL1 XTAL2 :2 1 PFD 0 Sine Wave Square Wave PLLRefDiv Prescaler 18 Bit DSM Charge Pump
: 2, :4
CP_OUT VCO VTUNE Logic Interface SDA SCL SADD
:2
0 CKREF_OUT 1
OUTRefDiv
102322_007
2.2
Downconverter and Baseband Filtering
The L band input from the LNB is fed into the CX24118A either differentially or single-ended. The input signal goes through a low-noise amplification block and is downconverted to a baseband frequency by quadrature downconversion. The output of the downconverter is band limited by a variable bandwidth filter that can be set to 35, 40, 65, or 100 MHz. A
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
15
NXP Semiconductors
CX24118A
Chapter 2: Functional Descriptions
variable gain baseband amplifier section provides further amplification. The baseband section includes a servo loop, which eliminates DC offset variations at the output. The baseband amplifier section also includes a filter with finer bandwidth control between 2 MHz and 65 MHz. The filter is optimized to provide stop band attenuation for anti-alias filtering and adjacent channel performance.
2.3
Gain Settings
The CX24118A is controlled by a single AGC signal, providing a dynamic range of 90 dB. The gain stages include an LNA (Low Noise Amplifier) and VCA (Voltage Controlled Attenuator), VGA1 (Variable Gain Amplifier 1), VGA2, and a final amplifier. These gain stages are shown in figure 2-1. The gain and offset of the different stages can be adjusted to provide the best overall IP3 and Noise Figure performance over input power. To optimize the performance at both high and low powers, split gain settings are recommended. This involves estimating the input power in order to select the best set of gain settings. The maximum signal level settings given in Table 2 should be used when the input power is high while there is significant power from other carriers within the satellite frequency range. The minimum signal level settings given in Table 3 should be used when the input power is low or when significant power from other carriers within the satellite frequency range does not exist. The transition point between the minimum signal level settings and the maximum signal level settings is set at Pthreshold = -50 dBm.
Table 2. Maximum Signal Level Settings
Parameter
RFVCAOff[1:0] BBVGA2Off[2:0] BBVGA1Off[2:0] BBAmpGain[3:0]
Register Location
0x20[3:2] 0x1F[5:3] 0x1F[2:0] 0x1D[3:0]
Register Setting
00b 111b 111b 0011b
Meaning
-70 dB -27 dB -22 dB 31 dB(1)
FOOTNOTES: (1) This value is valid for the CX24116, CX24126, and CX24114 demodulators. For the CX24123 demodulator, use the setting that corresponds to 25 dB.
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
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NXP Semiconductors
CX24118A
Chapter 2: Functional Descriptions
Table 3.
Minimum Signal Level Settings
Parameter
RFVCAOff[1:0] BBVGA2Off[2:0] BBVGA1Off[2:0] BBAmpGain[3:0]
Register Location
0x20[3:2] 0x1F[5:3] 0x1F[2:0] 0x1D[3:0]
Register Setting
10b 011b 010b 0011b
Meaning
-64 dB -29 dB -32 dB 31 dB(1)
FOOTNOTES: (1) This value is valid for the CX24116, CX24126, and CX24114 demodulators. For the CX24123 demodulator, use the setting that corresponds to 25 dB.
2.4
Local Oscillator and PLL
A bank of six Voltage Controlled Oscillators (VCOs) cover the entire 925 MHz to 2175 MHz range for downconversion with adequate overlap between VCOs. Each VCO has two bands of operation, high and low, resulting in a total of 12 virtual VCOs. All the VCOs are integrated into the chip, eliminating the need for external varactor diodes. The automatic tuning system selects the appropriate VCO to generate the Local Oscillator (LO), eliminating the need for calibration during initialization or channel change. The VCOs can also be selected manually, overriding the automatic tuning system. For more information on the automatic tuning system, see Section 2.6 The on-chip fractional synthesizer generates the LO with a very fine step size. The fractional synthesizer consists of a 9-bit integer divider and an 18-bit sigma delta modulator with an 8level quantizer. The sigma delta modulator dithers the fractional division ratio to convert spurious tones and quantization noise to white noise. The charge pump current selection is based on the VCO tuning voltage, i.e., VCO output frequency. The charge pump tuning system uses four tuning voltage ranges, and the charge pump current level for each range is set automatically at every channel change to give optimum integrated phase noise. The values to be programmed into the PLL's integer and fractional divider registers are computed as follows:
1. Set the dividers LODivSel (0x18[6]) and PLLRefDiv (0x02[1]) based on pre-defined or
calculated frequency ranges. * See Figure 3 for recommended divider settings when using a 40 MHz crystal.
2. Calculate the total PLL division ratio.
VCO Ndivider = --------------------- ; if PLLRefDiv = 0 VCO = --------------------- ; if PLLRefDiv = 1
F x1 F xtal x 2
F x2 F xtal x 2
3. Calculate the integer divider PLLIntDiv[8:0].
PLLIntDiv[8:0] = Round[Ndivider] - 32 * The Round function rounds the result to the nearest integer. * PLLIntDiv[8:0] can range from 6d to 511d. This is taken into consideration when selecting the divider ranges.
CX24118A_N_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
17
NXP Semiconductors
CX24118A
Chapter 2: Functional Descriptions
4. Calculate the fractional divider PLLFracDiv[17:0].
PLLFracDiv[17:0] = Round [218 x (Ndivider - PLLIntDiv[8:0] - 32)] * To avoid fractional spurs, the fractional divider should not produce VCO frequencies within 250 kHz or 125 kHz of the frequencies generated by PLLFracDiv[17:0] = 0.0 or 0.5 respectively. * When the requested frequency is within 250 kHz of the frequency generated by PLLFracDiv[17:0] = 0.0, the PLL should be put into integer mode. Integer mode is enabled by setting register bit DSMByp (0x10[6]) to 1. * When the requested frequency is within 125 kHz of the frequency generated by PLLFracDiv[17:0] = 0.5, the closest fractional value outside of the keep-out range should be used.
Figure 3. Recommended Divider Settings vs. Frequency When Using 40 MHz Crystal
/4 LODivSel (1) /2 Divider ratio /2 PLLRefDiv (2) /1
925
1165
f (MHz)
1500 (3)
2175
REN_003
(1)
The LO divider is changed to /4 below 1165 MHz in order to keep the VCO frequency out of the input frequency range of 925 to 2175 MHz. (2) The PLL frequency divider is changed across the frequency band to optimize phase noise while keeping the value of PLLInDiv[8:0] within its usable range of 65-511d. (3) This reference divider break-point is set at 37.5*Fxtal. For a 40 MHz Xtal, this value is 1500 MHz.
2.5
Crystal Oscillator and Reference Clock
The crystal oscillator should be used with a 40 MHz or 40.444 MHz third-overtone crystal. It generates the reference frequency for the fractional synthesizer and provides the clock for the rest of the system. It is also divided and buffered to produce an external clock that can be used as a clock signal for the demodulator. Register bit OutRefDiv (0x02[2]) sets the frequency of the reference clock output at pin CKREF_OUT so that when OUTRefDiv = 0, a
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CX24118A
Chapter 2: Functional Descriptions
40 MHz sinusoidal clock is produced, and when OUTRefDiv = 1, a 20 MHz square clock is produced (when OUTRefDiv = 1 mode is used, the XTAL_BIAS pin needs to be grounded). The third overtone crystal requires external circuitry to load the crystal properly at the thirdovertone frequency while suppressing the fundamental frequency. This circuit is shown in Figure 4, and the recommended component values are listed in Table 4. The external components should be RF type components (high Q) with good characteristics at 40 MHz.
Figure 4. Third-Overtone Crystal Oscillator External Circuit
To System CX24118A :2 1 0 XTAL_BIAS CKREF_OUT XTAL1 8 XTAL2 9 To Demodulator C3 C1 C2 L1 OUTRefDiv
6
XSEL 35
102322_014
Table 4.
Recommended Component Values for Third-Overtone Crystal Oscillator External Circuit
Component
C1 C2 C3 L1
Value
22 pF 56 pF 1 nF 390 nH
The selected crystal should be a high-quality crystal with minimum drive level dependencies. Table 5 lists the required crystal characteristics. Component tolerances should be 5 percent or better.
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CX24118A
Chapter 2: Functional Descriptions
Table 5.
Crystal Requirements
Parameter
Frequency Mode Frequency tolerance at 25 C Frequency tolerance over temperature Maximum equivalent series resistance (ESR) (1) Aging Load Capacitance Maximum Drive Level(2) Operating Temperature Range
Specification
40.000 MHz (40.444 MHz(3)) Parallel resonant, 3rd overtone 25 ppm 50 ppm 80 5 ppm/Year 18 pF 1 mW 0 C to 70 C
FOOTNOTES: (1) This is the maximum crystal series resistance for reliable startup at low energy levels. Compliance with this spec at 10 nW is required. This number is also required at operating power levels. (2) The power dissipated across the crystal will depend on the ESR of the crystal and the bias level of the oscillator. Leaving the XTAL_BIAS pin open will create a lower bias current than if it were shorted to ground. (3) A 40.444 MHz crystal is only needed when DVB symbol rates of 44-45 MSps are required for the CX24116 DVB-S2 demodulator.
2.6
Automatic Tuning System
The CX24118A uses an automatic tuning system to select the VCO and band during channel change. The system selects among the 12 virtual VCOs (VCO1-VCO6, each with a high and low band) based on preload values that are programmed during initialization. The automatic tuning system does not require time-consuming calibration during initialization or channel change. The procedure for using the automatic tuning system is given in Section 2.6.1.
2.6.1
Auto-tuning Procedure
During Initialization 1. Program the tuning system preload values with the values provided by Conexant and enable the automatic tuning system. a. Set register field TUN1[5:0] (0x14[5:0]) to 0x0F. - Register 0x14 also contains the tuning system enable bits, TUNAutoEn[1:0], which should be programmed to 00b at the same time. b. Set register TUN2[7:0] (0x15[7:0]) to 0xFF. c. Set register TUN3[7:0] (0x16[7:0]) to 0xFF. d. Set register TUN4[7:0] (0x17[7:0]) to 0xF0. 2. Program automatic charge pump levels with the values provided by Conexant. These values are selected based on the VCO tuning voltage. a. Set register field CPLevel1[1:0] (0x11[7:6]) to 11b. b. Set register field CPLevel2[1:0] (0x11[5:4]) to 11b. c. Set register field CPLevel3[1:0] (0x11[3:2]) to 10b.
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Chapter 2: Functional Descriptions
d. Set register field CPLevel4[1:0] (0x11[1:0]) to 00b. 3. There are other registers not directly related to tuning system initialization that must also
be programmed. These values are not discussed here.
During Channel Change 1. Choose the appropriate dividers using register bits LODivSel (0x18[6]) and PLLRefDiv (0x02[1])). For more detail, see Section 2.4 2. Select the gain settings. The minimum signal level settings can be used at this point. 3. Set the bandwidths of the baseband filters using register fields BBFil1BW[1:0] and BBFil2BW[1:0] based on the symbol rate, roll-off, and desired carrier acquisition range. 4. Program the PLL dividers PLLIntDiv[8:0] and PLLFracDiv[17:0] using the values generated from the procedure given in Section 2.4, and start the tuning process as follows: a. Program registers 0x19-0x1B. b. Program the remaining PLL dividers into register 0x1C while setting the start bit TUNReset (0x1C[4]) to 1. 5. Monitor PLL lock using register bit TUNLD. When lock has been achieved, measure the power to determine the appropriate gain settings. Set new gain settings if required. See Section 2.3 for more detail. a. After lock, the charge pump values are automatically selected, based on the VCO tuning voltage and the charge pump initialization values.
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Chapter 2: Functional Descriptions
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Chapter 3: Serial Programming Interface and Registers
Rev. 02 -- 8 September 2009 Product data sheet
3.1
Serial Programming Interface
The CX24118A uses an I2C-compatible serial interface. The serial clock and data lines, SCL and SDA, are used to transfer data at a clock rate of up to 1 MHz. A direct, exclusive connection is preferred between controlling master and the tuner slave. If the chip is put on a common I2C bus shared by other devices, the ongoing traffic on the bus may cause RF interference. Both lines operate on 3.3 V I/O voltage levels. The SDA line is open drain, requiring an external pull-up resistor. The serial clock and data signals for a typical transaction is shown in Figure 5.
Figure 5.
Serial Clock and Data Signals
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
MSB
LSB
SDA
Start Condition
(1)
(1)
Slave Address
Register Address
Data
(2)
FOOTNOTE:
(1) (2)
Acknowledge generated by CX24118A. Subsequent bytes are assumed to be data for registers whose addresses follow in ascending order.
102322_012
The START condition occurs on the falling edge of the SDA line when the SCL line is held high. A STOP condition occurs on the rising edge of the SDA line when the SCL line is held high. Every data word is 8 bits long with MSB first, followed by an acknowledge bit generated by the receiving device. Each data transaction occurs between a START and a STOP condition. The START condition is followed by a slave address. If this is the CX24118A address, it generates an acknowledge bit on the SDA line. The following are some typical read/write sequences:
Typical Single-Byte Write Procedure 1. Send the Start condition. 2. Send the CX24118A slave address, a write bit, and receive an ACK. 3. Send the CX24118A desired register address = n, and receive an ACK. 4. Send the byte for a desired register = n, and receive an ACK. 5. Send the Stop condition. The above-described single-byte write procedure is shown in Figure 6. In the figure, the following abbreviations are used: S = Start Dev Addr/wr = Device address with a write command A = Acknowledge P = Stop
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Stop Condition
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NXP Semiconductors
CX24118A
Chapter 3: Serial Programming Interface and Registers
Figure 6.
Typical Single-Byte Write Procedure
S
Dev Addr/wr
A
Reg. Address = n
A
Data (n)
A
P
Master
Slave
Master
Slave
Master
Slave
102322_008
Typical Multiple-Bytes Write Procedure 1. Send the Start condition. 2. Send the CX24118A slave address, a write bit, and receive an ACK. 3. Send the CX24118A desired register address = n, and receive an ACK. 4. Send the byte destined for register n, and receive an ACK. 5. Send the byte destined for register n+1, and receive an ACK. 6. Send the byte destined for register n+2, and receive an ACK. 7. Send the data destined for register n+m, and receive an ACK 8. Send the Stop condition. The above-described multiple-bytes write procedure is shown in Figure 7. In the figure, the following abbreviations are used: S = Start Dev Addr/wr = Device address with a write command A = Acknowledge P = Stop
Figure 7. Typical Multiple-Bytes Write Procedure
S
Dev Addr/wr
A
Reg. Address = n
A
Data (n)
A
Master
Slave
Master
Slave
Master
Slave
Data (n+1)
A
Data (n+2)
A
Data (n+m)
A
P
Master
Slave
Master
Slave
Master
Slave
102322_009
Typical Single-Byte Read Procedure 1. Send the Start condition. 2. Send the CX24118A slave address, a write bit, and receive an ACK. 3. Send the CX24118A desired register address = n, and receive an ACK. 4. Send the Start condition. 5. Send the part's slave address, a read bit, and receive an ACK. 6. Receive the byte from the desired register n, and do not supply an ACK.
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Chapter 3: Serial Programming Interface and Registers
7. Send the Stop condition.
NOTE:
When reading data from a slave, no ACK is supplied from master after the last desired byte.
The above-described single-byte read procedure is shown in Figure 8. In the figure, the following abbreviations are used: S = Start Dev Addr/wr = Device address with a write command A = Acknowledge P = Stop Dev Addr/r = Device address with a read command
Figure 8. Typical Single-Byte Read Procedure
S
Dev Addr/wr
A
Reg. Address = n
A
S
Dev Addr/rd
Master
Slave
Master
Slave
Master
A
Data (n)
A
P
Slave
Master
Slave
102322_010
Multiple-Bytes Read Procedure 1. Send the Start condition. 2. Send the CX24118A slave address, a write bit, and receive an ACK. 3. Send the CX24118A desired register address = n, and receive an ACK. 4. Send the Start condition. 5. Send the part's slave address, a read bit, and receive an ACK. 6. Receive the byte from register n, and supply an ACK. 7. Receive the byte from register n+1, and supply an ACK. 8. Receive the byte from register n+2, and supply an ACK. 9. Receive the data from register n+m, and do not supply an ACK. 10. Send the Stop condition.
NOTE: When reading data from a slave, no ACK is supplied from master after the last desired byte.
The above-described multiple-bytes read procedure is shown in Figure 9. In the figure, the following abbreviations are used: S = Start Dev Addr/wr = Device address with a write command A = Acknowledge P = Stop Dev Addr/r = Device address with a read command
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CX24118A
Chapter 3: Serial Programming Interface and Registers
Figure 9.
Typical Multiple-Bytes Read Procedure
S
Dev Addr/wr
A
Reg. Address = n
A
S
Dev Addr/rd
Master
Slave
Master
Slave
Master
A
Data (n)
A
Data (n+1)
A
Data (n+m)
A
P
Slave
Master
Slave
Slave
Master
102322_011
3.2
Registers
The register bit map is shown in Table 6.
Table 6.
Register Bit Map (Sheet 1 of 2)
D7 D6 D5 Global 00 01 02 Reserved Tuner 10 11 12 13 14 15 16 17 18 19 1A PLLIntDiv[0] VCOSel[5] LODivSel TUNAutoEn[1:0] TUN2[7:0] TUN3[7:0] TUN4[7:0] VCOSel[4:0] PLLIntDiv[8:1] PLLFracDiv[17:11] VCOBandSel DSMClkPol DSMByp CPMan[1:0] CPLevel2[1:0] BsDelayVal[3:0] CPDVal[1:0] CPLevel3[1:0] Reserved Reserved TUN1[5:0] CPCtrl TUNLD CPSel CHPId[7:0] CHPVer[7:0] OUTRefDiv PLLRefDiv Reserved D4 D3 D2 D1 D0
Register Address(1)
CPLevel1[1:0]
CPLevel4[1:0] CPVal[1:0]
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Chapter 3: Serial Programming Interface and Registers
Table 6.
Register Bit Map (Sheet 2 of 2)
D7 D6 D5 D4 D3 D2 D1 D0
Register Address(1) 1B 1C 1D 1E 1F 20 21
PLLFracDiv[10:3] PLLFracDiv[2:0] Reserved BBFil1BW[1:0] Reserved Reserved Reserved CPEn BBVGA2Off[2:0] RFVCABCDis PSEn RFVCAOff[1:0] BBEn DCCorrEn TUNReset Reserved BBFAmpGain[3:0] BBFil2BW[5:0] BBVGA1Off[2:0] Reserved Reserved RFVCAEn
FOOTNOTES: (1) The values in this column are hexadecimal.
3.3
Register Index
The register index is shown in Table 7.
Table 7.
Register Index
Field Name
BBEn BBFAmpGain[3:0] BBFil1BW[1:0] BBFil2BW[5:0] BBVGA1Off[2:0] BBVGA2Off[2:0] BsDelayVal[3:0] CHPId[7:0] CHPVer[7:0] CPCtrl CPDVal[1:0] CPEn CPLevel1[1:0] CPLevel2[1:0] CPLevel3[1:0] CPLevel4[1:0] 21[3]
Address(1)
Baseband Enable. Final Baseband Amplifier Gain. Baseband Filter 1 Bandwidth. Baseband Filter 2 Bandwidth. Baseband VGA1 Offset Control. Baseband VGA2 Offset Control. VCO Tuning System Delay. Chip Identification Number. Chip Version Number. Charge Pump Control. Digital Charge Pump Valve. Charge Pump Enable.
Description
1D[3:0] 1E[7:6] 1E[5:0] 1F[2:0] 1F[5:3] 12[7:4] 00[7:0] 01[7:0] 12[2] 10[3:2] 21[5] 11[7:6] 11[5:4] 11[3:2] 11[1:0]
Automatic Charge Pump Level 1 Select. Automatic Charge Pump Level 2 Select. Automatic Charge Pump Level 3 Select. Automatic Charge Pump Level 4 Select.
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Chapter 3: Serial Programming Interface and Registers
Table 7.
Register Index
Field Name
CPMan[1:0] CPSel CPVal[1:0] DCCorrEn DSMByp DSMClkPol LODivSel OUTRefDiv PLLFracDiv[17:0]
Address(1)
10[5:4] 10[0] 12[1:0] 21[2] 10[6] 10[7] 18[6] 02[2] 1A[6:0], 1B[7:0], 1C[7:5] 19[7:0], 1A[7] 02[1] 21[4] 20[4] 21[0] 20[3:2] 14[5:0] 15[7:0] 16[7:0] 17[7:0] 14[7:6] 10[1] 1C[4] 18[0] 18[7], 18[5:1]
Description
Manual Analog Charge Pump Select. Manual Override of Automatic Charge Pump Level Select. Analog Charge Pump Level. DC Offset Correction Enable. Delta Sigma Modulator Bypass. DSM Clock Polarity Select. Local Oscillator (LO) Divider Select. Output Reference Divider. PLL Fractional Divider.
PLLIntDiv[8:0] PLLRefDiv PSEn RFVCABCDis RFVCAEn RFVCAOff[1:0] TUN1[5:0] TUN2[7:0] TUN3[7:0] TUN4[7:0] TunAutoEn[1:0] TUNLD TUNReset VCOBandSel VCOSel[5:0]
PLL Integer Divider. PLL Reference Divider. Prescaler Enable. RF VCA Bias Control Circuit Disable. RF VCA Enable. RF VCA Offset Select. Tuning System Configuration Register 1. Tuning System Configuration Register 2. Tuning System Configuration Register 3. Tuning System Configuration Register 4. Auto-tuning System Enable. PLL Lock Detect. Tuning System Reset. VCO Band Select. VCO Select.
(1)
FOOTNOTES: The values in this column are hexadecimal.
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Chapter 3: Serial Programming Interface and Registers
3.4
Register Detail
This section provides the register detail.
NOTE: NOTE: POR refers to power-on reset value. All bits in the registers are Read/Write unless indicated otherwise in the bit description.
Register 00
Register (Hex) 00 CHPId[7:0] POR 43 D7 D6 D5 D4 CHPId[7:0] D3 D2 D1 D0
Chip Identification Number. The current chip ID is 0x23. Read only.
Register 01
Register (Hex) 01 CHPVer[7:0] POR 03 D7 D6 D5 D4 D3 D2 D1 D0
CHPVer[7:0]
Chip Version Number. The current chip version is 0x03. Read only.
Register 02
Register (Hex) 02 OUTRefDiv POR 00 D7 D6 D5 Reserved D4 D3 D2 OUTRefDiv D1 PLLRefDiv D0 Reserved
Output Reference Divider. This bit selects the reference clock divider for the CKREF_OUT pin. See Section 2.5 for more detail. 0 = /1. 1 = /2. PLL Reference Divider. This bit selects the divider for the tuner synthesizer reference frequency. 0 = /1. 1 = /2.
PLLRefDiv
Register 10
Register (Hex) 10 POR 00 D7 DSMClkPol D6 DSMByp D5 CPMan[1:0] D4 D3 CPDVal[1:0] D2 D1 TUNLD D0 CPSel
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Chapter 3: Serial Programming Interface and Registers
Register (Hex) DSMClkPol
POR
D7
D6
D5
D4
D3
D2
D1
D0
DSM Clock Polarity Select. 0 = No clock inversion. 1 = Clock inversion. Use this setting for normal operation. Delta Sigma Modulator Bypass. 1 = Disables the delta sigma modulator, resulting in integer division. 0 = Delta sigma modulator along with prescaler defines the divider. Normal operation. Manual Analog Charge Pump Select. Selection of analog charge pump level in manual mode when register bit CPSel is set to 1. The levels are defined as follows: 00b = 0.5 mA. 01b = 1.0 mA. 10b = 1.5 mA. 11b = 2.0 mA. Digital Charge Pump Valve. The digital charge pump is enabled during tuning only. 00b = 0.5 x analog charge pump level. 01b = 1.0 x analog charge pump level. 10b = 2.0 x analog charge pump level. Use this setting for normal operation. 11b = 3.0 x analog charge pump level. PLL Lock Detect. 0 = Synthesizer not frequency locked. 1 = Synthesizer is frequency locked. Manual Override of Automatic Charge Pump Level Select. 0 = Automatic charge pump current selection. 1 = Manual charge pump current selection.
DSMByp
CPMan[1:0]
CPDVal[1:0]
TUNLD
CPSel
Register 11
Register (Hex) 11 POR 00 D7 D6 D5 D4 D3 D2 D1 D0
CPLevel1[1:0]
CPLevel2[1:0]
CPLevel3[1:0]
CPLevel4[1:0]
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Chapter 3: Serial Programming Interface and Registers
Register (Hex) CPLevel1[1:0]
POR
D7
D6
D5
D4
D3
D2
D1
D0
Automatic Charge Pump Level 1 Select. Charge pump level 1 is selected by the automatic tuning system when the VCO tuning voltage is greater than 2.0 V. For normal operation, set to 11b. Automatic Charge Pump Level 2 Select. Charge pump level 2 is selected by the automatic tuning system when the VCO tuning voltage is between 1.5 V and 2.0 V. For normal operation, set to 11b. Automatic Charge Pump Level 3 Select. Charge pump level 3 is selected by the automatic tuning system when the VCO tuning voltage is between 1.0 V and 1.5 V. For normal operation, set to 10b. Automatic Charge Pump Level 4 Select. Charge pump level 4 is selected by the automatic tuning system when the VCO tuning voltage is lower than 1.0 V. For normal operation, set to 00b. For each of the above register fields, the analog charge pump levels are set as follows: 00b = 0.5 mA. 01b = 1.0 mA. 10b = 1.5 mA. 11b = 2.0 mA.
CPLevel2[1:0]
CPLevel3[1:0]
CPLevel4[1:0]
Register 12
Register (Hex) 12 BsDelayVal[3:0] POR 80 D7 D6 D5 D4 D3 Reserved D2 CPCtrl D1 CPVal[1:0] D0
BsDelayVal[3:0]
VCO Tuning System Delay. VCO tuning system delay in reference clock cycles between the time tuning system is enabled and tuning starts. The default is 8 counts and can be set between 0 and 15 counts of reference cycle. The reference cycle period is: TREF = R/Reference oscillator frequency R is the reference divider value selected by register bit PLLRefDiv (0x02[1]). For normal operation, set to 0x8.
CPCtrl
Charge Pump Control. 0 = Analog charge pump turns OFF when the digital charge pump turns ON (when register bit TUNLD (0x10[1]) is low). 1 = Analog charge pump always ON. Use this setting for normal operation. Analog Charge Pump Level. This is the value selected by the automatic tuning system, as specified in register 0x11. The values correspond to the following charge pump levels. Read only. 00b = 0.5 mA. 01b = 1.0 mA. 10b = 1.5 mA. 11b = 2.0 mA.
CPVal[1:0]
Register 14
Register (Hex) 14 POR 00 D7 D6 D5 D4 D3 TUN1[5:0] D2 D1 D0
TUNAutoEn[1:0]
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Chapter 3: Serial Programming Interface and Registers
Register (Hex) TUNAutoEn[1:0]
POR
D7
D6
D5
D4
D3
D2
D1
D0
Auto-tuning System Enable. 00b = Auto-tuning mode. The auto-tuning system selects the VCO. Normal operation. 01b = Manual tuning mode. The VCO is selected using register field VCOSel[5:0]. 10b - 11b = Reserved. Tuning System Configuration Register 1. For normal operation, set to 0x0F.
TUN1[5:0]
Register 15
Register (Hex) 15 TUN2[7:0] POR 00 D7 D6 D5 D4 TUN2[7:0] D3 D2 D1 D0
Tuning System Configuration Register 2. For normal operation, set to 0xFF.
Register 16
Register (Hex) 16 TUN3[7:0] POR 00 D7 D6 D5 D4 TUN3[7:0] D3 D2 D1 D0
Tuning System Configuration Register 3. For normal operation, set to 0xFF.
Register 17
Register (Hex) 17 TUN4[7:0] POR 00 D7 D6 D5 D4 TUN4[7:0] D3 D2 D1 D0
Tuning System Configuration Register 4. For normal operation, set to 0xF0.
Register 18
Register (Hex) 18 POR 00 D7 VCOSel[5] D6 LODivSel D5 D4 D3 VCOSel[4:0] D2 D1 D0 VCOBandSel
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Chapter 3: Serial Programming Interface and Registers
Register (Hex) VCOSel[5]
POR
D7
D6
D5
D4
D3
D2
D1
D0
VCO 6 Select. This bit, when read, indicates if VCO6 is selected. 0 = VCO 6 deselected. 1 = VCO 6 selected when VCOSel[4:0] = 00000b. Local Oscillator (LO) Divider Select. This bit, when read, indicates the LO divider selected by the auto-tuning system. When written to, this bit selects the divider. 0 = /2. 1 = /4. VCO Select. These bits, when read, indicate the VCO selected by the auto-tuning system. The VCO can be manually selected by writing to these bits. Only one VCO should be selected at a time. 00000b = None of these VCOs are selected. 00001b = VCO5 selected. 00010b = VCO4 selected. 00100b = VCO3 selected. 01000b = VCO2 selected. 10000b = VCO1 selected. VCO Band Select. This bit is common to all VCOs. This bit, when read, indicates the VCO band selected by the auto-tuning system. When written to, this bit selects the VCO band. 0 = High band. 1 = Low band.
LODivSel
VCOSel[4:0]
VCOBandSel
Register 19 - 1C
Register (Hex) 19 1A 1B 1C PLLIntDiv[8:0] PLLFracDiv[17:0] TUNReset POR 00 00 00 10 PLLFracDiv[2:0] PLLIntDiv[0] D7 D6 D5 D4 D3 D2 D1 D0
PLLIntDiv[8:1] PLLFracDiv[17:11] PLLFracDiv[10:3] TUNReset Reserved
PLL Integer Divider. PLL Fractional Divider. Tuning System Reset. Setting this bit to 1 resets the auto-tuning system and starts the auto-tuning process. Write only.
Register 1D
Register (Hex) 1D BBFAmpGain[3:0] POR 00 D7 D6 Reserved D5 D4 D3 D2 D1 D0
BBFAmpGain[3:0]
Final Baseband Amplifier Gain. 0000b = 37 dB gain. 0001b = 34 dB gain. 0011b = 31 dB gain. Use this setting under all conditions. 0111b = 28 dB gain. 1111b = 25 dB gain.
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NXP Semiconductors
CX24118A
Chapter 3: Serial Programming Interface and Registers
Register 1E
Register (Hex) 1E BBFil1BW[1:0] POR 00 D7 D6 D5 D4 D3 D2 D1 D0
BBFil1BW[1:0]
BBFil2BW[5:0]
Baseband Filter 1 Bandwidth. 00b = 100 MHz. 01b = 65 MHz. Use this setting for 30-45 MSps operation. 10b = 40 MHz. Use this setting for 20-30 MSps operation. 11b = 35 MHz. Use this setting for 1-20 MSps operation. Baseband Filter 2 Bandwidth. The filter bandwidth set is given by: BW = 2 + BBFil2BW[5:0] The bandwidth is adjustable in 63 steps with a step size of 1 MHz. The bandwidth range is 2 MHz to 65 MHz.
BBFil2BW[5:0]
Register 1F
Register (Hex) 1F BBVGA2Off[2:0] POR 00 D7 Reserved D6 D5 D4 BBVGA2Off[2:0] D3 D2 D1 BBVGA1Off[2:0] D0
Baseband VGA2 Offset Control. 000b = -41 dB. 100b = -39 dB. 010b = -37 dB. 110b = -35 dB. 001b = -33 dB. 101b = -31 dB. Use this setting when fixed gain settings are desired. 011b = -29 dB. Use this setting for minimum signal levels. 111b = -27 dB. Use this setting for maximum signal levels. Baseband VGA1 Offset Control. 000b = -36 dB. 100b = -34 dB. 010b = -32 dB. Use this setting for minimum signal levels. 110b = -30 dB. 001b = -28 dB. Use this setting when fixed gain settings are desired. 101b = -26 dB. 011b = -24 dB. 111b = -22 dB. Use this setting for maximum signal levels.
BBVGA1Off[2:0]
Register 20
Register (Hex) 20 POR 00 D7 D6 Reserved D5 D4 RFVCABCDis D3 D2 D1 Reserved D0
RFVCAOff[1:0]
CX24118A_N_2
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Product data sheet
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NXP Semiconductors
CX24118A
Chapter 3: Serial Programming Interface and Registers
Register (Hex) RFVCABCDis
POR
D7
D6
D5
D4
D3
D2
D1
D0
RF VCA Bias Control Circuit Disable. The VCA is made up of multiple, parallel, gain stages. When stages are unused, they are either turned off, or completely disabled by shutting off their bias, according to the state of this bit. 0 = Bias in unused stages is turned off. 1 = Bias in unused stages is not turned off. RF VCA Offset Select. 00b = -70 dB. Use this setting for maximum signal levels, and when fixed gain settings are desired. 01b = -67 dB. 10b = -64 dB. Use this setting for minimum signal levels. 11b = -61 dB.
RFVCAOff[1:0]
Register 21
Register (Hex) 21 CPEn POR 00 D7 Reserved D6 D5 CPEn D4 PSEn D3 BBEn D2 DCCorrEn D1 Reserved D0 RFVCAEn
Charge Pump Enable. 1 = Enable. 0 = Disable. Prescaler Enable. 1 = Enable. 0 = Disable. Baseband Enable. 1 = Enable. 0 = Disable. DC Offset Correction Enable. 1 = Enable. 0 = Disable. RF VCA Enable. 1 = Enable. 0 = Disable.
PSEn
BBEn
DCCorrEn
RFVCAEn
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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NXP Semiconductors
CX24118A
Chapter 3: Serial Programming Interface and Registers
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
36
CX24118A
Chapter 4: Application Information
Rev. 02 -- 8 September 2009 Product data sheet
4.1
Thermal Recommendations
The CX24118A uses a thermally enhanced QFN package with an exposed paddle underneath the device to dissipate heat. The exposed paddle is soldered directly to exposed PCB ground on the top layer of the board. Thermal vias then connect the top PCB layer to the other board layers. The more layers that are used, the better the thermal properties of the chip will be. Table 8 lists the CX24118A thermal layout recommendations.
Table 8. Thermal Recommendations
Parameter
Number of PCB layers(1) Numbers of thermal vias Thermal via spacing Solder mask opening under exposed paddle(2) Metallization land pattern Via diameter 2 or 4 16 (4x4 square matrix)
Recommendations
0.85 mm from center to center 3.7 x 3.7 mm 3.7 x 3.7 mm 0.33 mm drill-hole size with 1 oz copper plating.
FOOTNOTES: (1) As many of the layers should be grounded and connected to the thermal vias as possible. (2) Same as the package exposed paddle. The area outside the solder mask opening to the pin pads should be covered with solder mask.
4.2
4.2.1
Sleep Mode Procedures
Changing from Normal Operation to Sleep Mode
To change the tuner from normal operation to sleep mode, use the following procedure: 1. Set register field TUNAutoEn[1:0] (0x14[7:6]) to 01b. 2. Set register field VCOSel[5:0] (0x18[7] and 0x18[5:0]) to 0. 3. Set the system enable bits (0x21[5:0]) to 0x00.
4.2.2
Changing from Sleep Mode to Normal Operation
To change the tuner from sleep mode to normal operation, use the following procedure: 1. Set register field TUNAutoEn[1:0] (0x14[7:6]) to 01b. 2. Set the system enable bits (0x21[5:0]) to 0x3F. 3. Restart the tuning system by setting TUNReset to 1.
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
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NXP Semiconductors
CX24118A
Chapter 4: Application Information
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
38
CX24118A
Chapter 5: Electrical, Thermal, and Mechanical Specifications
Rev. 02 -- 08 September 2009 Product data sheet
5.1
Figure 10.
S11 Plot
S11 Plot
m1
m2
GENERAL NOTES: 1. m1 Frequency = 2.175 GHz S (1,1) = 0.626 / -119.116 Impedance = Z0 * (0.304 - j0.547) 2. m2 Frequency = 925.0 MHz S (1,1) = 0.482 / -84.258 Impedance = Z0 * (0.676 - j0.845), where Z0 = 50 3. The measurement was taken at the input of the device using a short 50 coaxial cable stub.
102322_015
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 08 September 2009
39
NXP Semiconductors
CX24118A
Chapter 5: Electrical, Thermal, and Mechanical Specifications
5.2
5.2.1
Table 9.
Electrical and Thermal Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings
Parameters
Supply voltage Input voltage range (digital) Storage temperature Junction temperature
Minimum
-0.3 -0.3 -65
Maximum
3.6 Vcc +150 +150
Units
V V
C C
5.2.2
Table 10.
Recommended Operating Conditions
Recommended Operating Conditions
Parameter
Ambient operating temperature Supply voltage
Minimum
0 3.13
Typical
+25 3.3
Maximum
+70 3.47
Units
C
V
5.2.3
Table 11.
Receiver Electrical and Thermal Specifications
Receiver Electrical Specifications (Sheet 1 of 3)
Parameter
Supply current Powerdown current(1) RF frequency Input power(2) LO leakage(4) Gain control voltage Maximum voltage gain
Conditions
Min
Typ
160 11
Max
240
Units
mA mA
925 -69 (-81) -80 0.1 At 1 MSps (Pin = -81 dBm) At 20 MSps (Pin = -70 dBm) At 45 MSps (Pin = -65 dBm) 77 66 61 90
2175 -23 (-6) -70 3
MHz dBm dBm Volts dB dB dB dB
AGC range Vout into minimum load of 500 single-ended or 1 k differential
Gain control voltage 0.5 to 2.5 V Single-ended
500
1000
mVpp
CX24118A_N_2
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Product data sheet
Rev. 02 -- 08 September 2009
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NXP Semiconductors
CX24118A
Chapter 5: Electrical, Thermal, and Mechanical Specifications
Table 11.
Receiver Electrical Specifications (Sheet 2 of 3)
Parameter
Harmonics on baseband outputs @ 1 Vpp output level (single-ended) I/Q phase balance I/Q amplitude balance Noise figure floor at minimum input level of -70 dBm Passband amplitude ripple at baseband output Group delay ripple at baseband output 170 kHz to 0.8 x f3dB
Conditions
Min
Typ
-30 3 1
Max
Units
dBc
5 3 12
Deg. dB dB dB ns ns ns dB dB dBm dBm dBm dBc dBc
SR = 20 MSps, filter BW = 18.5 MHz DC to 0.8 x f3dB(4) SR = 1 MSps f3dB = 3.175 MHz(5) SR = 20 MSps f3dB = 16 MHz(5) SR = 45 MSps f3dB = 33 MHz(5)
10 1 66 57 37 33 40
Stopband attenuation at 2 * f3dB(4) at baseband output Stopband attenuation at 3 * f3dB(4) at baseband output IIP3 (Out-of-band)(6) +(31 and 60) MHz, Pin = -30 dBm(8) +(91 and 180) MHz, Pin = -30 dBm(8) In-Band OIP3 (into 1 k load) Spurious rejection (2xLO - RF) wanted and interferer level set at -25dBm Spurious rejection (2xRF - LO) wanted and interferer level set at -25 dBm Thermal resistance of package jc: using two-layer board ja: using two-layer board jc: using four-layer board ja: using four-layer board -5 5.5 -1 -30 -40
10 10 18 -40 -45 7.2 47 4.8 31.5
C/W C/W C/W C/W
Serial Interface Specifications
Serial programming interface clock frequency Input voltage High logic voltage: VIH Low logic voltage: VIL 2.1 1.05 1 MHz V V
LO Specifications
CX24118A_N_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 08 September 2009
41
NXP Semiconductors
CX24118A
Chapter 5: Electrical, Thermal, and Mechanical Specifications
Table 11.
Receiver Electrical Specifications (Sheet 3 of 3)
Parameter
Operating VCO frequency Tuning step size @ 40 MHz fref Reference frequency Spurs Integrated DSB phase noise with 40 MHz reference frequency Lock time(8)
Conditions
Min
2330
Typ
Max
4660
Units
MHz Hz MHz
160 40 1 MHz to 40 MHz offset frequencies Integrated from 1 kHz to 1 MHz offset frequencies Between any two frequencies within the operating range of 925 MHz to 2175 MHz -40 -44 1 -30 -36 5
dBc dBc msec
Reference Oscillator Output Specifications
Reference oscillator output frequency(9) Reference oscillator output level Reference oscillator output DC offset FOOTNOTES: This is the current drawn when all blocks are disabled except the crystal oscillator and digital sections. (2) -25 dBm is single tone power and -6 dBm is the aggregate average power of 40 QPSK modulated carriers. -69 dBm is the minimum power at 20 MSps, and -81 dB is the minimum power at 1 MSps. (3) This LO leakage is at RF_INP pin from 925 MHz-2175 MHz.
(1) (4) (5) (6)
40 (20) 2 1.6
MHz Vp-p V
f3dB is the baseband bandwidth given by: ------- x ( 1 + alpha ) + LNB offset + -- x ( PLL step size )
SR 2
1 2
f3dB is calculated for alpha of 0.35, LNBoffset of 2.5 MHz. PLL step size, being very small (160 Hz), can be ignored. These IIP3 tone offsets are specifically for a symbol rate of 20 MSps, with the overall filter bandwidth set at 18.5 MHz and the bandwidth of the filter at the mixer output set at 35 MHz. The IIP3 tone offsets scale with symbol rate assuming a channel spacing of 1.5*SR. Thus the (31,60) MHz tones correspond to (1.5*SR, 3*SR) MHz and the (91,180) MHz tones correspond to (4.5*SR, 9*SR) MHz. (7) This level is derived assuming -23 dBm is the maximum level of all other transponders, an operating symbol rate of 20 MSps and a C/I of 7 dB. (8) From after serial communication has been received to stable lock. (9) The output level is across 10 k || 20 pF load. The output waveform is sinusoidal when register bit OUTRefDiv (0x02[2]) is set to /1, and is a square wave when OutRefDiv is set to /2.
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 08 September 2009
42
NXP Semiconductors
CX24118A
Chapter 5: Electrical, Thermal, and Mechanical Specifications
5.3
Mechanical Specifications
The CX24118A uses two 36-pin Quad Flat No-Lead (QFN) plastic packages. The CX24118A package diagrams are shown in Figure 11 and Figure 12.
Figure 11.
Package Diagram
D Pin 1 Indicator D1
4xP
b D2 Pin 1 Indicator
4xP
1
2
1 2 3
3
D
D1
D2
L
TOP VIEW e BOTTOM VIEW
See Detail A A2 A
Dim. A A1 A2 A3 D D1 D2 b e L P
All Dimensions in Millimeters Min. Nom. Max. ---0.00 ---0.85 0.01 0.65 0.20 REF . 6.00 BSC 5.75 BSC 3.70 0.23 0.50 BSC 0.60 0.42 ---0.90 0.05 0.70
Seating Plane
A3
A1
SIDE VIEW
3.55 0.18 0.50 0.24 ----
3.85 0.30 0.75 0.60 12O
102322_006
b A1
Detail A
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 08 September 2009
43
NXP Semiconductors
CX24118A
Chapter 5: Electrical, Thermal, and Mechanical Specifications
Figure 12.
Package Diagram
HVQFN36: plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; body 6 x 6 x 0.85 mm
SOT1092-2
D
B
A
terminal 1 index area
E
A
A1 c
detail X
e1 e 10 L 9 19 e b 18 v w CAB C y1 C
C y
Eh
e2
1 terminal 1 index area 36 Dh 28
27
X
0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 6.1 6.0 5.9 Dh 4.05 3.90 3.75 E(1) 6.1 6.0 5.9 Eh 4.05 3.90 3.75 e 0.5
2.5 scale e1 4 e2 4 L 0.65 0.55 0.45
5 mm
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18
0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT1092-2 References IEC JEDEC --JEITA --European projection
sot1092-2_po
Issue date 09-02-23 09-02-24
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 08 September 2009
44
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
Legal information
Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
CX24118A_N_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 September 2009
45
NXP Semiconductors
CX24118A
Advanced Modulation Digital Satellite Tuner
46
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 September 2009 Document identifier: CX24118A_N_2

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